Wire Bonding to Advanced Copper, Low-K Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations

There are three areas to consider when designing/implementing wire bonding to advanced ULSI damascene–copper chips having copper metallization and low dielectric-constant polymers embedded beneath them (Cu/LoK). These are: 1) the copper-pad top-surface oxidation inhibitor coatingmetal/organic/inorganic. (Current work involves evaluating the metal and inorganic options); 2) the low dielectric constant materials available; 3) under-pad metal/polymer stacks and support structures necessary for bondability and reliability. There are also various polymer/metallurgical interactions, resulting in long term packaged-device reliability problems, that can occur as the result of the wire bonding process over low modulus, LoK materials with barriers. These include cracked diffusion barriers, copper diffusion into the LoK polymers, cracking/spalling/crazing of the LoK materials, and bond pad indentation (“cupping”). Low-K polymer materials, with high expansion coefficients and low thermal conductivities, can also increase the stress and further extend any existing damage to barriers. Many of the above problems have previously been encountered when bonding to pads over polymers (MCM-D, polymer buildup-layers on PCBs, PBGAs, flex circuits, etc.), and they share some of the same solutions. Well designed LoK and the underpad structures should have no negative effect on bonding parameters and be invisible to the bonding process.